Language and Compiler for FPGA

This paper presents a high-level, algorithmic, single-assignment programming language and its optimizing compiler for reconfigurable systems. The compiler is capable of accepting our proposed instruction sets and generating a set of synthesizable VHDL codes. Simulated annealing algorithm at the heart of this compiler determines the design speed and resource needed on Field Programmable Gate Array (FPGA). Language features are introduced and the structure of the compiler is discussed. In the paper, we particularly study the effects of simulated annealing schemes on our compiler. Key-Words: High-level, single assignment, VHDL, FPGA, compiler and simulated annealing.